1. Field of the Invention
The present invention relates to semiconductor circuit devices, and more particularly, to a semiconductor memory device having a normal operation mode and a self refresh mode.
2. Description of the Background Art
FIG. 39 is a circuit diagram showing a partial structure of a conventional dynamic random access memory (referred to as DRAM hereinafter). Referring to FIG. 39, this DRAM includes a sense amplifier of a P channel sense amplifier 36 and an N channel sense amplifier 44, a pair of bit lines BL and /BL arranged at one side of the sense amplifier, another pair of bit lines BL and /BL arranged at the other side of the sense amplifier, a switch circuit 56 responsive to a bit line select signal BLI1 for connecting one of the pairs of bit lines BL and /BL to the sense amplifier, and a switch circuit 62 responsive to a bit line select signal BLI2 for connecting the other pair of bit lines BL and /BL to the sense amplifier.
More specifically, this DRAM employs a shared sense amplifier method. This sense amplifier selects one of the two pairs of bit lines BL and /BL disposed at either side to amplify the potential difference generated between the selected pair of bit lines BL and /BL.
FIG. 40 is a timing chart indicating an operation of the shared sense amplifier of FIG. 39. The potential is plotted along the ordinate, and time is plotted along the abscissa. As shown in FIG. 40, bit line pair BL and /BL is initially precharged to a level of an intermediate potential of (xc2xd) Vcc by a bit line equalize/precharge circuit 68, and a boosted power supply potential Vpp higher than a power supply potential Vcc is supplied to switch circuits 56 and 62 as bit line select signals BLI1 and BLI2, respectively. Accordingly, the pairs of bit lines BL and /BL at opposite sides are connected to the sense amplifier.
When a memory block B1, for example, is selected, only the potential of bit line select signal BLI2 falls from the level of boosted potential Vpp to ground potential GND. As a result, bit line pair BL, /BL in memory block B2 is disconnected from the sense amplifier, and only bit line pair BL and /BL in memory block B1 is connected to the sense amplifier.
When the potential of a word line WL rises from the level of ground potential GND to boosted power supply potential vpp, charge flows from a memory cell 30 connected to that word line WL towards bit line BL, whereby difference in potential occurs between one bit line BL and the other bit line /BL. Here, the potential of bit line BL is pulled up to the level of power supply potential Vcc by P channel sense amplifier 36, and the potential of bit line /BL is pulled down to the level of ground potential GND by N channel sense amplifier 44.
In a normal operation mode of a DRAM, bit line select signal BL1 is maintained at the level of boosted power supply potential Vpp until the potentials of bit lines BL and /BL reach the level of power supply potential Vcc and ground potential GND, respectively. Therefore, bit line pair BL and /BL is continuously connected to the sense amplifier until amplification of that bit line pair is completed. This operation of a shared sense amplifier is carried out, not only in a normal operation mode, but also in a self refresh mode.
FIG. 41 is a circuit diagram showing a structure of a conventional internal voltage-down circuit used in a DRAM. Referring to FIG. 41, the internal voltage-down circuit includes a reference potential generation circuit 182 for generating a constant reference potential Vref1, a voltage-down converter 164 that is always activated, and a voltage-down converter 190 that is selectively activated. In a standby mode, only voltage-down converter 164 of a low current supply capability operates. In an active mode, voltage-down converter 190 of a great current supply capability operates in addition to voltage-down converter 164. More specifically, when internal circuit 180 is activated in response to an internal row address strobe signal RASI, a comparator circuit 192 is also activated in response to internal row address strobe signal RASI. Therefore, the internal voltage-down circuit can supply a current of an amount greater than that of a standby state to internal circuit 180.
In a conventional internal voltage-down circuit, voltage-down converter 190 of a great current supply capability is activated in response to internal row address strobe signal RASI even in a self refresh mode as in a normal operation mode.
Although high speed of a level identical to that of a normal operation mode is not required in a self refresh mode, the operation of the shared sense amplifier in a self refresh mode is identical to that of a normal operation mode as shown in FIGS. 39 and 40. This means that a great amount of through current is conducted in the sense amplifier during an amplify operation of a bit line pair that is as much as in a normal operation mode even in a self refresh mode. Therefore, there is a problem that a great amount of power is consumed in a self refresh mode.
Furthermore, in a self refresh mode, the conventional internal voltage-down circuit of FIG. 41 has the voltage-down converter of a great current supply capability activated in response to internal row address strobe signal RASI as in a normal operation mode. Therefore, similar to a normal operation mode, a great amount of current is consumed even in a self refresh mode.
An object of the present invention is to provide a semiconductor memory device that can have power consumption reduced in a special operation mode in which the operation rate is lower than that of a normal operation mode.
Another object of the present invention is to provide a semiconductor circuit device that can have power consumption reduced in a special operation mode in which the operating rate is lower than that of a normal operation mode.
According to an aspect of the present invention, a semiconductor memory device with a normal operation mode and a special operation mode in which the operation rate is lower than that of the normal operation mode includes first and second sense nodes, a sense amplifier, first and second bit line pairs, a plurality of word lines, a row decoder, first and second switch elements, and a control circuit. The sense amplifier is connected to the first and second sense nodes, and amplifies the potential difference generated between the first and second sense nodes. The first bit line pair is arranged at one side of the sense amplifier. The second bit line pair is arranged at the other side of the sense amplifier. The plurality of word lines cross the first and second bit line pairs. The row decoder responds to a row address signal to selectively activate a word line. The first switch element is connected between the first and second sense nodes and the first bit line pair. The second switch element is connected between the first and second sense nodes and the second bit line pair. The control circuit controls the first and second switch elements so as to connect one of the first and second bit line pairs to the sense amplifier in a normal operation mode. In a special operation mode, the control circuit controls the first and second switch elements so that one of the first and second bit line pairs is connected to the sense amplifier, the connected bit line pair is disconnected from the sense amplifier after data is read out therefrom, and the disconnected bit line pair is connected to the sense amplifier again after the sense amplifier is activated.
In a special operation mode, preferably in a self refresh mode, a bit line pair is disconnected from the sense amplifier after data is read out thereto, followed by activation of the sense amplifier. Therefore, the potential difference between the first and second sense nodes is amplified speedily. The through current flowing across the sense amplifier in a special operation mode is smaller than that of a normal operation mode. As a result, power consumption in a special operation mode, preferably a self refresh mode, is reduced.
According to another aspect of the present invention, a semiconductor memory device with a normal operation mode and a special operation having an operation rate lower than that of a normal operation mode includes a bit line pair, a sense amplifier, and a first sense amplifier drive circuit. The sense amplifier includes a first common source node, a first N channel transistor, a second N channel transistor, a second common source node, a first P channel transistor, and a second P channel transistor. The first N channel transistor includes a source connected to the first common source node, a drain connected to one bit line of the bit line pair, and a gate connected to the other bit line of the bit line pair. The second N channel transistor includes a source connected to the first common source node, a drain connected to the other bit line of the bit line pair, and a gate connected to the one bit line of the bit line pair. The first P channel transistors includes a source connected to the second common source node, a drain connected to the one bit line of the bit line pair, and a gate connected to the other bit line of the bit line pair. The first P channel transistor includes a source connected to the second common source node, a drain connected to the other bit line of the bit line pair, and a gate connected to the one bit line of the bit line pair. The first sense amplifier drive circuit responds to a first sense amplifier drive signal for driving the sense amplifier by pulling down the potential of the first common source node to the level of ground potential at a first rate in a normal operation mode. In a special operation mode, the first sense amplifier drive circuit responds to a first sense amplifier drive signal for driving the sense amplifier by pulling down the potential of the first common source node towards the level of ground potential at a second rate higher than the first rate.
Preferably, the above semiconductor memory device further includes a second sense amplifier-drive circuit. The sense amplifier drive circuit responds to a second sense amplifier drive signal for driving the sense amplifier by pulling up the potential of the second common source node towards the power supply potential at a third rate in a normal operation mode. In a special operation mode, the second sense amplifier drive circuit responds to the second sense amplifier drive signal for driving the sense amplifier by pulling up the potential of the second common source node towards the power supply potential at a fourth rate higher than the third rate.
Since the potential of the first common source node is pulled down to the level of the ground potential at a rate slower than in the normal operation mode in a special operation mode, the through current flowing through the sense amplifier is smaller than that in a normal operation mode. In addition, the potential of the second common source node is pulled up towards the level of the power supply potential at a rate slower than in a normal operation in the special operation mode, so that the through current flowing through the sense amplifier is further reduced than in a normal operation mode. As a result, power consumption in a special operation mode is smaller than that in a normal operation mode.
According to a further aspect of the present invention, a semiconductor circuit device with a normal operation mode and a special operation mode having an operation rate slower than that of the normal operation mode includes an internal power supply line, an internal circuit, an internal power supply potential supply circuit, and an activation circuit. The internal circuit is connected to the internal power supply line, and is activated in response to a predetermined activation signal. The internal power supply potential supply circuit has a first supply capability, and a second supply capability greater than that of the first supply capability for supplying an internal power supply potential lower than an external power supply potential on the basis of the external power supply potential to the internal power supply line. The activation circuit responds to an activation signal for activating the internal power supply potential supply circuit at the second supply capability in a normal operation mode, and responds to an activation signal for activating the internal power supply potential supply circuit at the first supply capability in a special operation mode.
Since the internal power supply potential supply circuit is activated in a special operation mode at a supply capability smaller than that of the normal operation mode, power consumption in the special operation mode is lower than that of a normal operation mode.
According to still another aspect of the present invention, a semiconductor circuit device with a normal operation mode and a special operation mode of an operation rate slower than that of the normal operation mode, and having an internal circuit operated on the basis of a boosted power supply potential higher than a power supply potential includes a first transistor, a second transistor and a control circuit. The first transistor is connected between a boosted power supply node to which a boosted power supply potential is supplied and the internal circuit. The second transistor is connected between a power supply to which the power supply potential is supplied and the internal circuit. The control circuit causes the second transistor to maintain an OFF state and the first transistor to be turned on in a normal operation mode. The control circuit further causes the second transistor to attain an ON state for a predetermined time period and the first transistor to be turned at an elapse of the predetermined time period in a special operation mode.
In a normal operation mode, the potential supplied to the internal circuit is raised at one time from the level of ground potential to the boosted power supply potential. In contrast, the potential applied to the internal circuit is first raised from the level of ground potential to the power supply potential, and then from the level of the power supply potential to the boosted power supply potential in a normal operation mode. Since the potential is pulled up to the level of the power supply potential by the power supply in a special operation mode, power consumption is reduced than in a normal operation mode in which the potential is pulled up at one time to the boosted power supply potential.
According to a still further aspect of the present invention, a semiconductor memory device with a normal operation mode and a self refresh mode includes a plurality of memory block, and a select refresh circuit. Each of the plurality of memory blocks includes a plurality of word lines, a plurality of bit line pairs crossing the word lines, and a plurality of memory cells provided at a respective crossings of a word line and a bit line pair. The select refresh circuit selectively refreshes a memory block including a memory cell storing data out of the plurality of memory blocks.
In a self refresh mode, a memory block in which no data is stored is not refreshed. Only a memory block storing data is refreshed. Therefore, power consumption is reduced in comparison to the case where all memory blocks are refreshed.
According to yet a further aspect of the present invention, a semiconductor memory device with a normal operation and a self refresh mode includes a plurality of word line groups, a word line drive signal generation circuit, a predecoder, a plurality of decoder units, and first and second shift registers. Each of the plurality of word line groups includes a plurality of word lines. The word line drive signal generation circuit responds to a portion of an internal address signal in a normal operation mode for generating a plurality of word line drive signals corresponding to the plurality of word lines. The predecoder responds to the other portion of the row address signal in a normal operation mode for generating a predecode signal. The plurality of decoder units are provided corresponding to the plurality of word line groups, and are selectively activated in response to a predecode signal in a normal operation mode. Each decoder unit responds to a word line drive signal for selectively activating a word line of a representative word line group. The first shift register selectively activates the plurality of decoder units sequentially in a self refresh mode. The second shift register selectively activates the plurality of word line drive signals sequentially in a self refresh mode.
In a self refresh mode, the first shift register selectively activates the plurality of decoder units sequentially, and then selectively activates the plurality of word line drive signals sequentially. It is therefore not necessary to generate a predecode signal for activating a word line. This means that the charge/discharge current for generating a predecode signal is not required. As a result, power consumption in a self refresh mode is reduced.
According to yet another aspect of the present invention, a semiconductor memory device with a normal operation mode and a self refresh mode includes first and second memory blocks, a series of sense amplifiers, a plurality of first and second switch elements, and a control circuit. Each of the first and second memory blocks includes a plurality of bit line pairs. The series of sense amplifiers include a plurality of sense amplifiers between the first and second memory blocks, and corresponds to the plurality of bit line pairs. The plurality of first switch elements are provided corresponding to the plurality of bit line pairs in the first memory block. Each first switch element is connected between a corresponding bit line pair and a sense amplifier. The plurality of second switch elements are provided corresponding to the plurality of bit line pairs in the second memory block. Each second switch element is connected between a corresponding bit line pair and a sense amplifier. The control circuit controls the first and second switch elements so that a bit line pair in one of the memory blocks to be selected is continuously connected to the sense amplifier and a bit line pair in the other memory block not selected is disconnected from the sense amplifier in response to every row address signal applied thereto in a normal operation mode. In a self refresh mode, the control circuit controls the first and second switch elements so that, when a memory block to be selected in response to a currently applied row address signal is identical to the memory block that is already selected in response to the prior applied row address signal, a bit line pair in the memory block to be selected is continuously connected to the sense amplifier, and the bit line pair of the other memory block that is not selected is disconnected from the sense amplifier, and otherwise, the bit line pair in the one memory block that is to be selected is connected to the sense amplifier, and the bit line pair in the other memory block that is already selected is disconnected from the sense amplifier.
When the same memory block is continuously selected in a self refresh mode, the bit line pair in that memory block remains connected to the sense amplifier. Therefore, power consumption is reduced in comparison with the case where a bit line pair is disconnected from the sense amplifier at every selection of a memory block.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.